As the technology node continues to shrink to produce smaller and smaller integrated circuit transistor devices, it is becoming increasingly challenging to fabricate and make electrical contact to the terminals of each transistor device. One concern is preventing the inadvertent formation of a short between the transistor gate and the transistor source-drain regions when using raised source-drain epitaxial regions. Another concern is preventing the inadvertent formation of a short between adjacent active regions. Circuit designers must include sufficient spacing between devices to avoid the risk of shorting, but this solution comes at the expense of increased surface area. This area penalty can be especially problematic in designs which utilize unmerged source-drain structures for adjacent transistor devices.
A need accordingly exists in the art for an improved process for fabricating transistor devices that can address concerns with source-drain epitaxial shorting, self-alignment of source-drain contacts while maintaining reduced contact resistance, and the formation of source-drain contacts self-aligned to the gate.